The present invention relates to a semiconductor device, and more particularly, to a test entry circuit and a method for generating a variety of test entry signals for performing respective test modes at a wafer level.
A semiconductor device such as a double data rate synchronous DRAM (DDR SDRAM) has a variety of test modes to screen unstable circuits in the device. The test modes include a wafer test mode for performing a test at a wafer level, and a package test mode for performing a test at a package level after the wafer test.
The wafer test mode is divided into a wafer burn-in test mode and a wafer normal test mode according to the object of the test mode.
The wafer burn-in test mode is performed to screen semiconductor devices having defects generated during the fabrication process. In the wafer burn-in test mode, a stress is applied to drive the semiconductor device with a high drive voltage at a high temperature to thereby find unstable factors in the semiconductor device. As such, the wafer burn-in test mode makes it possible to reduce unnecessary package cost and improve final test yield.
The wafer normal test mode is performed to determine whether the functions and performances of the semiconductor device meet the specifications of the semiconductor design or not. In the wafer normal test mode, probing pins of a test apparatus are electrically connected to pads to apply predetermined voltage to the pads or receive desired voltage from the pads. Consequently, by performing the predetermined operations according to the normal test mode, it is possible to improve the product completeness and reduce the development time. In addition, the normal test mode is also performed to reduce the number of probing pins required for the test. For example, in a case where a signal of a logic high level is applied to first and second pads for the normal test mode, the number of probing pins for each semiconductor device can be reduced by connecting the first and second pads inside the chip and applying the signal of the logic high level to the first and second pads through a single probing pin.
FIG. 1 is a block diagram of a conventional test entry circuit.
Referring to FIG. 1, the conventional test entry circuit includes a first pad 110, a burn-in test entry signal generator 130, a second pad 150, a normal test entry signal generator 170 and a power up signal generator 190 connected to external power supply voltage VDD and ground VSS.
The burn-in test entry signal generator 130 receives a burn-in test signal WBI through the first pad 110 to generate a burn-in test entry signal WBI_EN. The normal test entry signal generator 170 receives a normal test signal WNM through the second pad 150 to generate a normal test entry signal WNM_EN.
The burn-in test signal WBI is activated in a burn-in test mode, and the normal test signal WNM is activated in a normal test mode.
The power up signal generator 190 detects a voltage level of the external power supply voltage VDD to generate a power up signal PWRUPb. As the voltage level of the initial external power supply voltage VDD increases, the voltage level of the power up signal PWRUPb also increases. However, if the voltage level of the external power supply voltage VDD exceeds a desired target level, the voltage level of the power up signal PWRUPb is fixed to a logic low level. The burn-in test entry signal generator 130 and the normal test entry signal generator 170 are initialized in response to the power up signal PWRUPb.
FIG. 2 is a circuit diagram of the burn-in test entry signal generator 130 shown in FIG. 1.
Referring to FIG. 2, the burn-in test entry signal generator 130 includes a first output unit 210 and a first initialization unit 230. The first output unit 210 generates the burn-in test entry signal WBI_EN in response to the burn-in test signal WBI. The first initialization unit 230 initializes an input node of the first output unit 210 in response to the power up signal PWRUPb.
As the voltage level of the external power supply voltage VDD increases, the first initialization unit 230 is enabled to initialize an input node of the first output unit 210 to a logic low level. Then, the first output unit 210 outputs the burn-in test entry signal WBI_EN of a logic low level. When the power up signal PWRUPb changes to a logic low level, the first initialization unit 230 terminates the initialization. When the burn-in test signal WBI changes to a logic high level to start the burn-in test mode, the first output unit 210 outputs the burn-in test entry signal WBI_EN of a logic high level. Then, the semiconductor device enters the burn-in test mode in response to the burn-in test entry signal WBI_EN.
FIG. 3 is a circuit diagram of the normal test entry signal generator 170 shown in FIG. 1.
Referring to FIG. 3, the normal test entry signal generator includes a second output unit 310 and a second initialization unit 330. The second output unit 310 generates a normal test entry signal WNM_EN in response to a normal test signal WNM. The second initialization unit 330 initializes an input node of the second output unit 310 in response to a power up signal PWRUPb.
Operations of the normal test entry signal generator 170 are similar to those of the burn-in test entry signal generator 130. The second initialization unit 330 is enabled in response to a power up signal PWRUPb. Then, the second initialization unit 330 initializes an input node of the second output unit 310 to a logic low level, so that the second output unit 310 outputs the normal test entry signal WNM_EN of a logic low level. When the normal test signal WNM changes to a logic high level to start the normal test mode, the second output unit 310 outputs the normal test entry signal WNM_EN of a logic high level. Then, the semiconductor device enters the normal test mode in response to the normal test entry signal WNM_EN.
Referring again to FIG. 1, the first pad 110 is configured to receive the burn-in test signal WBI, and the second pad 150 is configured to receive the normal test signal WNM.